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Computer Architecture (AC)

Credits Dept. Type Requirements
9.0 (7.2 ECTS) AC
  • Compulsory for DIE
  • Elective for DCSFW
  • Elective for DCSYS
 EC2 - Prerequisite for DIE , DCSYS , DCSFW
EST - Prerequisite for DIE , DCSYS , DCSFW
SO - Prerequisite for DIE , DCSFW

Instructors

Person in charge:  (-)
Others:(-)

General goals

Upon finishing this subject, students should be able to carry out quantitative assessments, using figures of merit, of the performance of a processor running a program. They should also come away with an understanding of the following:
-  Concurrence techniques-which are easy to understand for the machine code programmer-used in processors in order to reduce processing time.
-  Applications of code restructuring techniques (instruction planning) for providing support to instruction latency.
-  Some of the restrictions of current technology and forecasts for the future.

Specific goals

Knowledges

  1. Importance of evaluating features in order to justify alternatives.
  2. Segmentation and parallelism (parallel processing).
  3. Dependence (precedence).
  4. The concept of risk.
  5. Prediction and speculation concepts.



    Hardware mechanisms for reducing latency in the execution of instructions.



    Renumber - concept.



    Hardware-software compromises.

Abilities

  1. Quantitative evaluation of performance.
  2. Analysis of and changes to data paths.
  3. Evaluation of data path delays and their relationship to cycle time.
  4. Building temporal interaction diagrams for interpreting instructions in a processor employing segmentation and parallelism.
  5. Understanding compiler-generated code and the scope for making code changes affecting the calculation performed.

Competences

  1. Introduction to compression and description of processor micro-architecture.
  2. Evaluation of processor performance.
  3. Learning and comprehension of the mechanisms and concepts bearing on the course content but which are not explicitly taught.
  4. Learning and comprehension of new concepts regarding the future of a processor micro-architecture.

Contents

Estimated time (hours):

T P L Alt Ext. L Stu A. time
Theory Problems Laboratory Other activities External Laboratory Study Additional time

1. Von-Neumann Architecture and performance
T      P      L      Alt    Ext. L Stu    A. time Total 
4,0 4,0 2,0 0 2,0 6,0 0 18,0








  • Laboratory
    Learning a simulation tool. Summary of the workings and basic characteristics of the elements making up the data path in a single-cycle processor.



  • Additional laboratory activities:
    Reading of and answers to the questions arising from lab measurements.

2. Techniques for increasing the number of operations per unit of time
T      P      L      Alt    Ext. L Stu    A. time Total 
4,0 2,0 0 0 0 10,0 0 16,0

3. Linearly-segmented scalar processor
T      P      L      Alt    Ext. L Stu    A. time Total 
6,0 5,0 8,0 0 8,0 20,0 0 47,0








  • Laboratory
    Data path in a linearly-segmented processor and the semantic fit of a segmented processor to machine language semantics. The use of segmentation to enhance processor performance.







  • Additional laboratory activities:
    Reading of and answers to the questions arising from lab measurements.

4. Scalar processor with multicycle operations
T      P      L      Alt    Ext. L Stu    A. time Total 
4,0 3,0 0 0 0 12,0 0 19,0

5. Software techniques for reducing data and sequencing risks
T      P      L      Alt    Ext. L Stu    A. time Total 
3,0 2,0 0 0 0 8,0 0 13,0

6. Superescalar processor
T      P      L      Alt    Ext. L Stu    A. time Total 
4,0 3,0 0 0 0 10,0 0 17,0

7. Prediction applied to sequencing instructions
T      P      L      Alt    Ext. L Stu    A. time Total 
3,0 2,0 0 0 0 8,0 0 13,0

8. Processor with anticipatory instruction scheduling
T      P      L      Alt    Ext. L Stu    A. time Total 
6,0 4,0 0 0 0 12,0 0 22,0

9. Speculative execution, perspectives and trends
T      P      L      Alt    Ext. L Stu    A. time Total 
2,0 1,0 0 0 0 3,0 0 6,0

10. Simulation tool
T      P      L      Alt    Ext. L Stu    A. time Total 
0 0 3,0 0 0 0 0 3,0








  • Laboratory
    Learning a simulation tool. Summary of the workings and basic characteristics of the elements making up the data path in a single-cycle processor.


Total per kind T      P      L      Alt    Ext. L Stu    A. time Total 
36,0 26,0 13,0 0 10,0 89,0 0 174,0
Avaluation additional hours 5,0
Total work hours for student 179,0

Docent Methodolgy

Classes building up concepts in a structured fashion and setting out the commitment required for their practical application.







Classes focusing on individual work in order to consolidate concepts, skills and competencies.







Lab classes focusing on co-operative work in order to consolidate concepts, skills and competencies.

Evaluation Methodgy

A) Individual final written exam on concepts, skills and competencies.



B) Individual final written test on the concepts, skills and competencies acquired.



C) Evaluation of co-operative work in connection with selected concepts, skills and basic competencies.



Final Grade = max(0.70 x A + 0.15 x B, 0.85 x A) + 0.15 x C

Basic Bibliography

  • John L. Hennessy, David A. Patterson Computer architecture : a quantitative approach, Elsevier, Morgan Kaufmann, 2007.
  • David A. Patterson, John L. Hennessy Organizaciķn y diseņo de computadores : la interfaz hardware/software, McGraw-Hill, 1994.

Complementary Bibliography

  • Capilano Computing Systems, Ltd LogicWorks 4 : interactive circuit design software, Addison-Wesley, 1999.

Web links

(no available informacion)

Previous capacities

Logic circuits: combinational and sequential logic circuits.

Programming, representation of elementary, structured data.

The workings of a computer: components and how they are interconnected.

Understanding machine language.

The workings of memory hierarchy and supporting devices.

The processor's external communication and supporting devices.

Basic statistic calculation.

Suggested prerequisites: EC2, Statistics, Operating Systems.


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